1. Field of the Technology
The present invention relates generally to digital communications, and more particularly to methods and apparatus for reducing a sampling rate during a sampling phase determination process.
2. Description of the Related Art
A wireless communication device, such as a mobile station operating in a wireless communication network, may provide for both voice telephony and packet data communications. The mobile station may, for example, be compatible with 3rd Generation (3G) communication standards (e.g. IS-2000) or utilize Global System for Mobile Communications (GSM), Time Division Multiple Access (TDMA), or Code Division Multiple Access (CDMA) wireless technologies.
All such communications utilize radio frequency (RF) signal detection techniques in a wireless receiver. Here, RF signals are received through an antenna, amplified, and demodulated to recover a digital baseband signal having a symbol or chip period of T. In CDMA or direct sequence spread spectrum (DSSS) communications, each symbol is referred to as a “chip.” The baseband signal is sampled by an analog-to-digital converter having a sampler which samples the signal at a sampling period which is determined by a sampling clock signal. Assuming that a phase of the sampling clock signal can be finely adjusted in time so that sampling will occur at the appropriate sampling time instant, user or signaling information may be adequately recovered by sampling the baseband signal at a sampling period of T (i.e. a sampling frequency or rate of 1/T) which may be the same as the symbol or chip period T of the baseband signal.
To find the appropriate phase of the sampling clock signal and thus the optimal sampling time point, a sampling phase determination process is performed. The sampling phase determination process typically involves oversampling (i.e. sampling at a sampling rate greater than 1/T) the baseband signal by n samples per modulation symbol. The value of n may be 4 or 8, for example, so that the baseband signal may be oversampled by as much as 4 or 8 times (e.g. sample period=T/n=T/4 or T/8). Correlation techniques are then utilized to identify an optimal or maximum correlation result associated with the appropriate phase. Subsequently, the baseband signal is down-sampled at the sampling period of T at the appropriate phase identified from the sampling phase determination process to recover the user or signaling information. This process may be repeated during communications to ensure that the sampling clock signal continues to be set at an appropriate phase.
In a typical CDMA or DSSS receiver, a searcher is used to determine a signal delay by correlating samples of the baseband signal with a local pseudorandom noise (PN) code. Once the delay of the PN code and the corresponding baseband signal that produces the strongest correlation is found, PN code synchronization, bit boundary synchronization, the sampling phase determination process are carried out. During the sampling phase determination process, each sample set of phase n of the oversampled baseband signal is correlated with the local PN. Amongst n correlator outputs, the signal associated with the maximum correlation result is associated with the appropriate phase. Usually n is between 4 and 16, depending on the shaping filter and spreading gain.
A delay locked loop (DLL) may be utilized in lieu of the CDMA searcher to obtain a fine determination and tracking of the optimal sample phase, where three correlators (i.e. an early correlator, an on-time correlator, and a late correlator) correlates the PN code with three sample phases of I-Q signals. Feedback is utilized to adjust the delay of the samples until the early and late correlators produce the same output level and the on-time correlator produces the highest output level. For TDMA and other non-CDMA communications, a timing estimation loop is typically utilized to adjust the sampling time in accordance with a criterion that maximizes the “eye-diagram opening.” Such schemes also utilize oversampling techniques. In lieu of any of the above-described techniques, a sampling rate greater than twice the signal bandwidth may be utilized according to the Shannon sampling theorem or Nyquist principle, so that optimal sampling points between available samples may be interpolated.
In high bandwidth communication systems (e.g. wireless local area network (WLAN) such as 802.11b), high sampling rates require more expensive hardware (e.g. analog-to-digital converter, digital processing unit, and/or buffer memory) and higher power consumption. For a low-cost, handheld mobile device utilizing one or more batteries or a battery pack, these properties are undesirable. Accordingly, what are needed are methods and apparatus for reducing a sampling rate during a sampling phase determination process so as to overcome the deficiencies in the prior art.